1. Field of the Invention
This invention pertains to the field of memory systems, and more particularly, to a memory system and a method in which an operating mode is set using a multi-bit address signal.
A claim of priority is made under 35 U.S.C § 119 to Korean Patent Application No. 2003-70311, filed on 9 Oct. 2003, the entirety of which is hereby incorporated by reference.
2. Description of the Related Art
Certain memory systems are generally capable of operating under a variety of different operating modes, such as different data strobe modes, different data burst lengths, different CAS latencies, and so on. Accordingly, the memory systems typically include a mode register set (MRS) for programming and setting various operating modes for the memory system.
As background, a conventional memory will be described with reference to FIGS. 1–5.
FIG. 1 is a block diagram of a conventional memory system 10 with a memory device 30 and a memory controller 20. Generally, command and address information are supplied from the memory controller 20 to the memory 30, and data is passed therebetween in response to the command and address information.
FIG. 2 shows a data processing block diagram of a conventional memory device 30. As shown, the memory device 30 includes input buffers 40, 50, Mode Register Set (MRS) Generator 60, Command Decoder 70, Row Address Buffer 80, Column Address Buffer 90, Internal Column Address Generator 100, Row Decoder 110, Column Decoder 120, Burst Length Counter 130, Memory Cell Array 140, Sense Amplifier 150, and Data Input/Output Buffer 160. The operation of these processing blocks is described in more detail below.
FIG. 3 shows the relationship between an address signal MA (having bits 1:n) and the contents of an MRS table. As shown, the address bits MA, which are supplied from the memory controller 20, are used to set various operating modes such as DLL reset, test mode (TM), CAS Latency (CL), burst type (BT), and burst length (BL).
FIG. 4 illustrates an MRS command sequence whereby the memory controller 20 communicates burst length mode to the memory device 30. During a power-up sequence, the memory controller 20 communicates an MRS command 170 to the memory device 30. Although not shown, this is done by setting a corresponding combination of logical values for command lines typically designated as CS_BAR, RAS_BAR, CAS_BAR, and WE_BAR. Meanwhile, the bits MA<0:m> and MA<m+1:n> bits of the mode address signal communicated during the MRS command sequence via the address lines ADDER<0:m> and ADDR<m+1:n>, respectively, and communicate various operating mode parameters of the memory device 30 shown in FIG. 3. In the example of FIGS. 3 and 4, the bits A2, A1 and A0 of the address signal are 0, 1, 0 when the MRS command 170 is issued during power-up, and accordingly, the burst length is set to 4Later, during normal operation, another MRS command is issued with the bits A2, A1 and A0 of the address signal being 0, 0, 1, and accordingly, the burst length is changed to 2.
The general operation of functional blocks of FIG. 2 will now be described with respect to the setting of a burst length. The Command Decoder 70 decodes the MRS Command from the corresponding combination of logical values of the CS_BAR, RAS_BAR, CAS_BAR, and WE_BAR lines. In response to detecting an MRS Command, the Command Decoder 70 sets an MRS signal or flag to enable the MRS Generator 60 to receive the mode address signal communicated via the ADDR<0:m> and ADDR<m+1:n> address lines. The corresponding operating mode parameters are then stored in the MRS table of the memory device 30.
One such operating mode parameter of the memory device 30 is the burst length (BL). The “burst length” indicates the number of continuous operations (e.g., data reads and data writes) performed in a data burst mode. For example, when BL=4, in response to a data READ command four consecutive data read operations are performed, even though only one memory address is provided from the memory controller 20 to the memory device 30.
When the memory controller 20 wants to read or write data to or from the memory cell array 140, it sends a corresponding memory access (READ or WRITE) command to the memory device 30, together with a row address and a column address on the address lines ADDR<0:n>. The memory controller 20 indicates the READ and WRITE commands by setting corresponding combinations of logical values for the CS_BAR, RAS_BAR, CAS_BAR, and WE_BAR lines, which are in turn decoded by the Command Decoder 70. The row and column addresses received by the memory device 30 via the address lines ADDR<0:n> are buffered by input buffers 40 and 50, and supplied to the Row Address Buffer 80 and Column Address Buffer 90, respectively. The Row Address Buffer 80 generates a row address RA.
Meanwhile, the MRS Generator 60 provides a burst length selection signal MRS_BLi to the Burst Length Counter 130. The burst length selection signal MRS_BLi is generated corresponding to the burst length BL communicated from the memory controller 20 to the memory device 30 and stored in the MRS register, as generally discussed above and specifically shown in FIG. 4. The Burst Length Counter 130 uses the burst length selection signal MRS_BLi to count a desired burst period (e.g., BL=4) and generates a burst stop signal BS as a flag signal at the end of the specified burst period. The Burst Length Counter 130 provides the BS signal to the Internal Column Address Generator 100. The Internal Column Address Generator 100 also receives the column address CA. So long as the BS signal is active, the Internal Column Address Generator 100 generates an internal column address signal PCA<0:m>. The Internal Column Address Generator 100 provides the internal column address signal PCA<0:m> to the Column Address Buffer 90 which uses it to generate a column address CA.
The Row Decoder 110 receives the row address RA and generates therefrom a decoded row address, or word line WL, to activate a corresponding word line of the memory cell array 140. Similarly, the Column Decoder 120 receives the series of column address signals CA, corresponding to the burst length, and generates therefrom decoded column addresses, or column select lines CSL, to activate corresponding column lines of the memory cell array 140. The data is input/output from the memory cell array via sense amplifier 150 and data input/output buffer 160.
FIG. 5 illustrates how data is addressed in the Memory Cell Array 140 via the word line WL from the Row Decoder and the series of column select lines CSL corresponding to the burst length (e.g., BL=4).
Meanwhile, sometimes it is desired or necessary to change an operating mode of the memory device 30 in the memory system 10 after it has been initially set during the power-up sequence. For example, it may be desired or necessary to change the burst length from BL=4 to BL=2In that case, in the conventional memory system 10, it is necessary for the memory controller to issue another MRS command to the memory device 30 and to communicate a new set of operating mode parameters to be stored in the MRS table.
However, the repetition of MRS commands is inefficient and decreases the effective operating speed of the memory system 10.
Accordingly, it would be advantageous to provide a method and memory system that can select or change an operating mode of the memory device without issuing a new MRS command. Other and further objects will appear hereinafter.